Open Access Open Access  Restricted Access Subscription Access

Design and implementation of Arithmetic Unit using Vedic Multiplier

Vinyas K S, K. B. Ramesh

Abstract


The Arithmetic Logic Unit (ALU) is an essential part of digital computing that performs arithmetic and logical operations. The goal of this study is to improve computational efficiency, especially in multiplication operations, by investigating the integration of dedicated multiplier circuits inside the ALU architecture. The design and implementation of a logic unit utilizing Vedic multiplier principles offer a promising avenue for advancing the efficiency and performance of digital circuits. By harnessing ancient mathematical wisdom in modern computing applications, this research contributes to the ongoing pursuit of innovative and sustainable solutions in the field of digital design and engineering. The design and implementation of a logic unit utilizing Vedic multiplier principles offer a promising avenue for advancing the efficiency and performance of digital circuits. By harnessing ancient mathematical wisdom in modern computing applications, this research contributes to the ongoing pursuit of innovative and sustainable solutions in the field of digital design and engineering.


Full Text:

PDF

References


Shreyas Kapare, Ganesh Shinde, Maithili Andhare, Vijayalaxmi Kumbar “Create a 32-bit Vedic Multiplier and Compare it Against Other Multipliers Using A Carry LookAhead Adder” 2024 4th International Conference for Emerging Technology (INCET).

Bini Palas P, Priya Dharshni R, Rashida Tayiba S “Design and Analysis of 16-bit Vedic Multiplier using UT Sutra of Vedic Mathematics” 2023 International Conference on Innovative Data Communication Technologies and Application (ICID).

Akshobhya Jamadagni K R, Sumanth Sakkara, and Komal M “A Novel, Scalable N*N Reversible Logic Multiplier Design” 2022 3rd International Conference on Intelligent Engineering and Management (ICIEM).

Priti Gangwar, Ritik Gupta, and Gurjit Kaur “A Design Technique for Delay and Power Efficient Dadda-Multiplier” 2021 Third International Conference on Inventive Research in Computing Applications (ICIRCA).

Ashish.S.Phuse, Pankaj.P.Tasgaonkar “Design and Implementation of Different Multiplier Techniques and Efficient MAC Unit on FPGA” 2022 International Conference on Signal and Information Processing (IConSIP).

V. Priyanka Brahmaiah, Vijaya Kumar Gurrala, Sai Teja Tuduru “DESIGN OF AREA AND POWER-OPTIMIZED VLSI ARCHITECTURE OF ALU DESIGN USING SIGNED MULTIPLIER” 2022 International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems (ICMACC).

Hemanshi Chugh, Sonal Singh “Design and Implementation of a High-Performance 4-bit Vedic Multiplier Using a Novel 5-bit Adder in 90nm Technology” 2022 10th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO).

Gadda, Nilam; Eranna, U. (2020). [IEEE 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)]- 64-bit ALU Design using Vedic Mathematics.

G. Surekha, Gajula Madesh, Mamidisette Pavan Kumar, Hrushikesh Sriramoju “Design and Implementation of Arithmetic and Logic Unit (ALU)” 2023 2nd International Conference on Applied Artificial Intelligence and Computing (ICAAIC).

J.L.V Ramana Kumari, Varshitha Y, Rakesh M, Gopi Ch “DESIGN AND IMPLEMENTATION OF ALU USING RING COUNTERS” 2023 International Conference on Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT).


Refbacks

  • There are currently no refbacks.